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Chip package and method for fabricating the same [(10)I311365]

[Category : - ELECTRONICS]
[Viewed 83 times]

A chip package including a carrier, a chip, multiple conductive bumps, and multiple bonding posts is provided. The carrier has a carrying surface, an opposite back surface, and multiple plating through holes connecting the carrying surface and the back surface. Each plating through hole has a conductive wall for connecting circuit in different layers of the carrier. The chip has an active surface for bonding to the carrying surface of the carrier and multiple pads disposed on the active surface and corresponding to the plating through holes. In addition, the conductive bumps are respectively disposed on the pads and are embedded into the plating through holes. The bonding posts are disposed in the plating through holes respectively to connect the conductive bumps and the conductive walls, wherein the bonding posts and the bonding posts are made of the same material. Furthermore, a method for fabricating the chip package is provided.

Patent publications:

TW 200739847

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rayfw (Taiwan)

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