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Chip fabrication technique [(10)CN101853819B]

[Category : - ELECTRONICS]
[Viewed 85 times]

The invention relates to a process for manufacturing a chip, comprising: providing a wafer which has a first surface and a second surface opposite to each other, then forming a plurality of blind holes on the first surface of the wafer, forming an insulation layer and a plating seed layer which covers the insulation layer on the first surface and in the hole walls of the blind holes, forming a pattern mask on the plating seed layer above the first surface, then forming a conductive material in the blind holes to form a plurality of conductive blind holes in a plating manner, and forming a plurality of stress buffer rings on partial plating seed layer above the first surface, wherein the blind holes are respectively arranged in the stress buffer rings; finally removing the pattern mask and the partial plating seed layer under the pattern mask.

Patent publications:

CN 101853819

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rayfw (Taiwan)

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