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Semiconductor package structure [(10) CN102263079 B]

[Category : - ELECTRONICS]
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The invention discloses a semiconductor package structure, which includes a carrier, a chip, a plurality of bonding wires and a packaging colloid. The carrier includes a die pad, a plurality of engagement pins and a reinforced pin. The engagement pins and the reinforced pin are arranged around the die pad. Each engagement pin is provided with a first inner surface and a first outer surface. The reinforced pin is provided with a second inner surface and a second outer surface. The surface area of the second outer surface of the reinforced pin is larger than the surface area of the first outer surface of each engagement pin. The bonding wires are arranged between the chip and the first inner surfaces of the engagement pins and between the chip and the second inner surface of the reinforced pin. The packaging colloid is configured to coat the chip, the bonding wires, the first inner surfaces of the engagement pins and the second inner surface of the reinforced pin, and expose the first outer surfaces of the engagement pins and the second outer surface of the reinforced pin.

Patent publications:

CN 201110199759

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rayfw (Taiwan)

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