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Package structure and package process

[Category : - ELECTRONICS]
[Viewed 210 times]

A package structure and a package process are proposed by using pillar bump to connect an upper second chip and through silicon vias of a lower first chip, by which a gap between the first chip and the second chip can be controlled by adjusting a height of the pillar bumps. In other words, the pillar bumps can compensate the height difference between the first chip and the molding compound around the first chip so as to ensure the bondibility between the pillar bumps and the corresponding through silicon vias and improve the process yield. Furthermore, the pillar bumps can maintain the gap between the second chip and the molding compound such that an underfill can be successfully filled into the space between the first chip and the second chip.

Patent publications:

TW 2010116089

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rayfw (Taiwan)

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