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Semiconductor packaging structure and manufacturing method

[Category : - ELECTRONICS]
[Viewed 237 times]

The invention relates to a semiconductor packaging structure. The semiconductor packaging structure comprises a redistribution layer, at least one chip and at least one pin, wherein the redistribution layer has a power source input end and a power source output end, the chip is arranged on the redistribution layer and has an active surface, the active surface is in electrical connection with the redistribution layer, a power source input pad of the active surface of the chip is in connection with the power source output end of the redistribution layer correspondingly, the pin is arranged on the redistribution layer, the pin has a connection portion, a first convex portion and a second convex portion, the connection portion connects the first convex portion with the second convex portion, the first convex portion is in electrical connection with the power source input end of the redistribution layer correspondingly, and the second convex portion is in electrical connection with the power source output end of the redistribution layer correspondingly. The pin realizes providing a relatively large contact area, a relatively large cross section area and a prolonged conduction path and can realize an electric buffering effect when a power source is inputted into the chip through the redistribution layer to avoid damage to the chip.

Patent publications:

CN 103337486

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rayfw (Taiwan)

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