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Semiconductor package assembly and manufacturing method thereof

[Category : - ELECTRONICS]
[Viewed 148 times]

The invention relates to a semiconductor package assembly and a manufacturing method thereof. The semiconductor package assembly comprises a first chip, an intermediate layer base plate, a second chip, a package body and a signal line. The first chip is provided with an active surface and a nonactive surface which are relative. The intermediate layer base plate is provided with a first surface, a second surface and a signal conductive hole, wherein the first surface and the second surface are relative, and the second surface is arranged on the active surface of the first chip. The second chip is arranged on and is electrically connected with the first surface of the intermediate layer base plate. The package body covers a first chip, a second chip and an outer side surface, and the signal conductive hole of the intermediate layer base plate is exposed out of the outer side surface of the package body. The signal line is arranged on the outer side surface of the package body and is electrically connected with the exposed active surfaces of the signal conductive hole and the first chip.

Patent publications:

CN 102738120

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rayfw (Taiwan)

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